Electrical & Computer Engineering

Temperature Dependant Characteristics of Scaled NMOS Transistors with Ultra-thin High-K Dielectrics and Metal Gate Electrodes

In order to maintain the continuous scaling of CMOS devices, high-K dielectrics and metal gate electrodes have been used at ITRS (International Technology Roadmap for Semiconductor) 45nm technology node. In this paper, we discuss the temperature dependence of the threshold voltage, electron mobility and gate leakage current for the scaled NMOS transistor, which has an interfacial SiO2 layer (0.5nm) and an ALD (Atomic Layer Deposition) fabricated HfO2 dielectric layer (2.0nm) with a 10nm TiN metal gate electrode covered by polysilicon. Our analysis indicates both the threshold voltage and the electron mobility decrease with increasing the temperature, and the metal workfunction decreases at a rate of ~ 10-4 eV/K. Gate leakage current increases with the temperature, which will increase power consumption at high temperature.

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Wednesday, December 12th, 2007 Electrical & Computer Engineering, Physics Comments Off

A Quantum Mechanical Model of Gate Leakage Current for Scaled NMOS Transistors with Ultra-thin High-K Dielectrics and Metal Gate Electrodes

The continuous scaling of the gate insulator layer thickness in CMOS devices leads to excessive gate leakage current and device reliability problems. High-K material has been used to achieve equivalent electrical thickness with thicker physical thickness to reduce the gate leakage and improve the device performance at ITRS (International Technology Roadmap for Semiconductor) 45nm technology node. In this paper, we have investigated the gate leakage current by considering both direct tunneling (DT) and trap-assisted tunneling (TAT) quantum mechanically for a scaled NMOS transistor, which has an interfacial SiO2 layer (0.5nm) and an ALD (Atomic Layer Deposition) fabricated HfO2 dielectric layer (1.6nm) with a 10nm TiN metal gate electrode covered by polysilicon. In our simulations, we conclude 80% of the current is carried by DT and 20% of the current is carried by TAT. Gate leakage current varies with dielectric layer thickness, and DT current is more sensitive to the physical thickness compared with TAT current. The proper control of the interfacial layer is important to continue CMOS device scaling.

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Wednesday, December 12th, 2007 Electrical & Computer Engineering, Physics Comments Off

Mechanical Limitations of Materials for Steel Foil Based Flexible Electronics

This work investigates mechanical limitations of thin film materials on steel foil substrates for flexible electronic applications. A three layer structure consisting of 100 μm thick stainless steel foil as the substrate, followed by 1 μm thick spin-on-glass passivation layer and 0.3 μm thick patterned aluminum interconnect layer on top with varying widths between 10- 35 μm. A collapsing radius test method was adopted for the bending experiment and an elliptical curve fit was used to facilitate the strain measurement. The failure strain of aluminum interconnect layer was detected by monitoring the continuity of the test circuit during the experiment. The corresponding results reveal that the passivation layer cracked at a tensile strain of 0.46% and delaminated at a compressive strain of 0.68%. The metal interconnect layer ruptured at a tensile strain of 1.26% and delaminated from the substrate at a compressive strain of 1.22% due to the delamination of the passivation layer underneath. The steel foil substrate was plastically deformed at the relative small strain of 0.13%. The flexibility of steel foil based electronics can be effectively improved by using thinner foil substrates.

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Monday, November 26th, 2007 Electrical & Computer Engineering Comments Off

Rapid Convective Deposition Of Microsphere Monolayers For Fabrication Of Microlens Arrays

Micron-sized microspheres were deposited into thin films via rapid convective deposition using a similar method to that studied by Prevo and Velev, Langmuir, 2003. By varying deposition rate and contact angle, the optimal operating ranges in which 2D closed-pack of silica existed were obtained. Using a confocal laser scanning microscope, dynamic self-assembly of colloidal particles under capillary force during solvent evaporation was revealed. The resulting microstructure is controlled by varying the macroscale parameters and interaction between substrate and colloidal particles played an important role in formation of ordered crystalline arrays. Using the same technique, stacked layers of 1 micron silica monolayer on top of 1.1 micron polystyrene monolayers and subsequent melting of the polystyrene to partially wet the silica microspheres were deposited on GaN layer. This process was implemented on the top p-GaN layer of InGaN quantum wells light emitting diode (LEDs) device structure, resulting in the formation of a microlens array for enhancing its light extraction efficiency. This approach led to ~230% increase of the LEDs output power.

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Saturday, November 3rd, 2007 Chemical Engineering, Electrical & Computer Engineering Comments Off

Design of unidirectional subwavelength slit coupler for THz surface plasmons

In this paper, we demonstrate a unidirectional subwavelength slit coupler at THz frequencies by using two-dimensional finite difference time domain (FDTD) modeling. The near-field light emitted from the narrow slit serves as a subwavelength-scaled excitation source. By placing a particular grating structure on one side of the slit, the light could be guided in only one direction. This unidirectional subwavelength slit coupler is amenable to incorporation into optical integrated circuits at THz frequencies.

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Monday, September 24th, 2007 Electrical & Computer Engineering Comments Off