At the ITRS 45nm technology node, NMOS transistors with high-K dielectrics have an effective oxide thickness (EOT) less than 1nm. Electron mobility in these devices is affected by quantization of carrier energy and a redistribution of carriers at the semiconductor and gate dielectric interface due to the decrease of the gate dielectric layer thickness and the increase of substrate doping. Electron mobility is also affected by surface roughness and Coulomb scattering rising from the interface traps and fixed charges in the high-K layer. We develop a quantum mechanical model for electron mobility, including Coulomb scattering of carriers and surface roughness in scaled high-K, metal-gate, NMOS transistors, which predicts an increase in Coulomb scattering mobility and a slow decrease of surface roughness mobility with increasing the gate voltage. The total mobility is limited by the bulk mobility because of the need for highly-doped substrates for scaled 45nm node transistors.
Tags: Coulomb Scattering, High-K, Metal Gate, Mobility, Quantum Mechanical, Surface Roughness
In order to maintain the continuous scaling of CMOS devices, high-K dielectrics and metal gate electrodes have been used at ITRS (International Technology Roadmap for Semiconductor) 45nm technology node. In this paper, we discuss the temperature dependence of the threshold voltage, electron mobility and gate leakage current for the scaled NMOS transistor, which has an interfacial SiO2 layer (0.5nm) and an ALD (Atomic Layer Deposition) fabricated HfO2 dielectric layer (2.0nm) with a 10nm TiN metal gate electrode covered by polysilicon. Our analysis indicates both the threshold voltage and the electron mobility decrease with increasing the temperature, and the metal workfunction decreases at a rate of ~ 10-4 eV/K. Gate leakage current increases with the temperature, which will increase power consumption at high temperature.
Tags: Gate Leakage, High Temperature, High-K, Metal Gate, Mobility, Threshold Voltage
The continuous scaling of the gate insulator layer thickness in CMOS devices leads to excessive gate leakage current and device reliability problems. High-K material has been used to achieve equivalent electrical thickness with thicker physical thickness to reduce the gate leakage and improve the device performance at ITRS (International Technology Roadmap for Semiconductor) 45nm technology node. In this paper, we have investigated the gate leakage current by considering both direct tunneling (DT) and trap-assisted tunneling (TAT) quantum mechanically for a scaled NMOS transistor, which has an interfacial SiO2 layer (0.5nm) and an ALD (Atomic Layer Deposition) fabricated HfO2 dielectric layer (1.6nm) with a 10nm TiN metal gate electrode covered by polysilicon. In our simulations, we conclude 80% of the current is carried by DT and 20% of the current is carried by TAT. Gate leakage current varies with dielectric layer thickness, and DT current is more sensitive to the physical thickness compared with TAT current. The proper control of the interfacial layer is important to continue CMOS device scaling.
Tags: Direct Tunneling, Gate Leakage, High-K, Metal Gate, Quantum Mechanical, Trap-assisted Tunneling